1. Field of the Invention
This invention relates to a process and apparatus for simultaneous treatment of a surface of an integrated circuit structure using a remote plasma source to generate radicals, and spatially selective heating of portions of the surface with a light source such as a laser beam.
2. Description of the Related Art
Modification of the structure of surfaces of substrates such as a silicon wafer is needed at various steps or stages of CMOS transistor fabrication. For example, removal of contaminants and particles embedded in silicon wafer surfaces can be carried out by cleaning the wafer surface using the well known RCA cleaning process (using, sequentially, aqueous basic and acidic solutions). Such cleaning steps are critical prior to diffusion or oxide growth processes, although these cleaning steps normally result in the formation of undesirable native oxides on the cleaned surfaces. To ensure the absence of native oxides on cleaned silicon wafers, an HF-last process that forms H—Si bonds is frequently used.
If a thin layer of silicon nitride is needed on the surface of the cleaned silicon wafer, this can be achieved using an NH3 anneal, resulting in the formation of nitrides through chemical reactions during the anneal.
Direct plasma nitridation (DPN) and remote plasma nitridation (RPN), on the other hand, have been used for implanting nitrogen radicals into ultra-thin SiO2, either during its growth through ozone (O3) plasma oxidation, or after the growth of the films, to form silicon oxynitride.
Formation of a protective liner or barrier layer, such as a Ta/TaN or TiN layer to separate copper filler material from dielectric material in a via or trench interconnect, requires prior cleaning to remove the oxidized copper metal surface. An account of such different surface modification techniques, their applications, their advantages and shortcomings is given in Table 1 below:
TABLE 1SURFACE STRUCTURE MODIFICATION TECHNIQUESCOMMONLY USED IN CMOS FABRICATIONMODI-FICATIONSAD-DIS-APPLI-TECHNIQUEFEATURESVANTAGESVANTAGESCATIONSChemical:Wet, lowLowAbrasive,GeneralRCA, HF-lasttemperaturetemperature,cannotsurfacecan resultcontrol finalcleaningin cleansurfacesurfacesstructureeasily; weakstructures,may not beable to formcertainbondingsThermal: NH3HighCan form aDiffusing ofSurface prepanneal, formingtemperature,variety ofdopants andbefore highgas annealinvolvesbondings,result ink depositiondiffusionrepairundesirablestructuredopantdefects;profiles; highreducedthermaldefectbudget anddensitymay result inchemicalreactionsbetweendifferentmaterialsPlasma: DirectDirectExcitedSevereSiONplasmaplasmaatomic/ionic/surfaceformationnitridationcouplingmoleculardamage,DPNspecies thatuncontrolledcan formimplantation,bondingsundesirablewith wafersub-surfacesurfacesbondformation,need thermalactivation tocompletebondformationPlasma:DownstreamExcitedNeedSiONRemote Plasmaplasmaatomic/ionic/thermalformationNitridationcouplingmolecularactivation toRPNspecies thatcompletecan formbondbondingsformationwith wafersurfacesRF preclean forAr sputteringPhysical ionRIERF precleanliner Ta/TaN orsputtering tosputteringfor liner Ta/TiN depositionremove theattacks theTaN or TiNoxidizedlow K,depositionmetal surfacebowing(Cu) forprofile andback end lineresultingprocessingdifficulty for(BEOL)plug fillinterconnect(electricalplating). Inaddition,RIE plasmacan result incharge togate damage
Furthermore, wet process steps, dry processing steps, and thermal anneal, when used with the same wafer, requires manual removal of the wafer from one apparatus to another apparatus, e.g., transfer of the wafer from a wet processing apparatus to a vacuum apparatus. Such transfer steps would expose wafers to atmosphere and slow down the overall efficiency of the processing of the wafer.
With the introduction of new materials and architectural changes in the forth coming CMOS transistors, new challenges have been imposed on development of novel surface structure modification techniques. Examples of these challenges include the following.
High k Dielectrics-Si Substrate Interface
The structure of the interface between high K dielectrics and Si substrates is known to be difficult to control since chemical reactions between the dielectrics and the substrate tend to occur during film deposition and subsequent thermal treatments. This results in high equivalent oxide thickness (EOT) high density of state, high interface charge, threshold voltage instability and lower channel mobility in transistors. To minimize the reactions, it is necessary to grow an ultra-thin buffer layer (e.g., 1 mono-layer) of a known chemically inert compound, such as Si nitride, silicon oxynitride, or silicon oxide, before the deposition of the dielectrics without raising the overall EOT of the dielectric. This highly controlled surface modification technique is yet to be developed.
High k Dielectrics-Electrodes Interface
The highly controlled surface modification technique is also required to engineer the interface layer between metal gate electrode and high-k dielectrics. It has been found that the interfacial bonding reactions, interfacial stability, fixed charges have significant impact on metal gate work function, threshold voltage control, EOT, and device drive current.
Strained Si-Substrate Interface
Strained Si is normally fabricated by growing Si epitaxially on a substrate with slightly different lattice parameters, e.g., SiGe. One requirement of the substrate is that it should be completely free of contaminants, particles, native oxides, and structural defects before Si epitaxial growth or structural defects, such as vacancies, dislocations, inclusions, and twins, will exist at the Si to substrate interface and results in the relaxing of strains. Current surface cleaning techniques can eliminate surface contaminants, particles, and native oxides but cannot control the surface structural features.
Back End of Line (BEOL) RF Preclean
RF clean showed effective clean method for the BEOL interconnect. However, when the ions hit the bottom of the via holes, they are reflected back and damage the sidewall. In addition, some of the ions can directly hit the sidewall and damage the sidewall. To reduce the metal line-to-line capacitance, low K materials have been used for the inter metal dielectric (IMD). The weak structure of the low K dielectric material make them very susceptible to damage by high energy ions.
Prior art FIGS. 1-3 show, in FIG. 1, a trench profile 10 after the trench formation in silicon substrate 2. FIG. 2 then shows trench profile 10 of FIG. 1 after a conventional prior art RF preclean and deposition of liner 12, showing, at 14, serious bowing of the trench profile. With such bowing of the sidewalls of the trench, and the reduced metal line width, subsequent electroplating is more difficult, resulting in the start of void formation in the prior art structure of FIG. 2, as shown at 16 in FIG. 3.
It would, be desirable to provide a process for treatment, including cleaning and activation, of a substrate surface capable of being utilized with a number of different materials in the same apparatus.